Electrostatic discharge (ESD) protection circuits are used to protect integrated circuits from damage due to electrostatic discharge. FIG. 1 shows an existing ESD protection circuit 100, comprising a P-channel field effect transistor (PFET) 104, a buffer 108, and an R-C network 112. The R-C network 112 includes a resistor 136 and a capacitor 140. The ESD protection circuit 100 is connected to an integrated circuit 102.
The buffer 108 may be implemented by two inverters (not shown in FIG. 1). The source terminal 116 of the PFET 104 is connected to a source voltage 120, and the drain terminal 124 of the PFET 104 is connected to a ground 128. The PFET 104 includes a gate terminal 132 capable of receiving a low voltage from the buffer 108 to turn on the PFET 104 or a high voltage from the buffer 108 to turn off the PFET 104.
The source voltage 120 is susceptible to electrostatic discharge in the form of short duration, high voltage pulses. During normal operation, the capacitor 140 is charged to approximately equal to the source voltage (e.g., 3.3V) at a node 144, which causes the buffer 108 to supply a high voltage (e.g., 3.3V) to the gate terminal 132. The high voltage at the gate terminal 132 causes the PFET 104 to be turned off.
When electrostatic discharge occurs at the source voltage 120, the capacitor voltage, i.e., voltage at the node 144, remains at approximately the ground level temporarily, causing the buffer 108 to supply a low voltage to the gate terminal 132. The low voltage at the gate terminal 132 turns on the PFET 104, which allows the electrostatic discharge to flow through the PFET 104 thereby protecting the integrated circuit 102. When the capacitor 140 is charged back up to approximately the source voltage level (e.g., 3.3 V), causing the buffer 108 to supply a high voltage to the gate terminal 132, thereby turning off the PFET 104. The time period required by the capacitor 140 to be charged back up is based on the R-C time constant of the R-C network 112. A disadvantage of the circuit 100 is that the maximum operational voltage is limited to the voltage rating of the components, i.e., the buffer 108, the PFET 104 and the capacitor 140.